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| UTC BT169 SCR DESCRIPTION The UTC BT169 is glass passivated, sensitive gate thyristors in a plastic envelope, intended for use in general purpose switching and phase control applications. These devices are intended to be interfaced directly to microcontrollers, logic integrated circuits and other low power gate trigger circuits. 1 TO-92 1:CATHODE 2:GATE 3:ANODE QUICK REFERENCE DATA PARAMETER Repetitive peak off-state voltages Average on-state current RMS on-state current Non-repetitive peak on-state current SYMBOL VDRM, VRRM IT(AV) IT(RMS) ITSM MAX(B) 200 0.5 0.8 8 MAX(D) 400 0.5 0.8 8 MAX(E) 500 0.5 0.8 8 MAX(G) 600 0.5 0.8 8 UNIT V A A A ABSOLUTE MAXIMUM RATINGS PARAMETER Repetitive peak off-state voltages : SYMBOL VDRM,VRRM CONDITIONS MIN MAX B:200 D:400 E:500 G:600 UNIT V Average on-state current RMS on-state current Non-repetitive peak on-state current IT(AV) IT(RMS) ITSM Half sine wave; Tlead<=83C All conduction angles t=10ms t=8.3ms half sine wave; Tj=25C prior to surge t=10ms ITM=2A;IG=10mA; dIG/dt=100mA/s 0.5 0.8 8 9 A A A I2t for fusing Repetitive rate of rise of on-state current after triggering Peak gate current Peak gate voltage Peak reverse gate voltage I2t DIT/dt IGM VGM VRGM 0.32 50 1 5 5 A2 S A/s A V V UTC UNISONIC TECHNOLOGIES CO., LTD. 1 UTC BT169 PARAMETER Peak gate power Average gate power Storage temperature Operating junction temperature SCR SYMBOL PGM PG(AV) Tstg Tj Over any 20 ms period -40 CONDITIONS MIN MAX 2 0.1 150 125 UNIT W W C C THERMAL RESISTANCES PARAMETER Thermal resistance junction to lead Thermal resistance junction to ambient SYMBOL Rth j-lead Rth j-a CONDITIONS pcb mounted; lead length=4mm MIN TYP 150 MAX 60 UNIT K/W K/W ELECTRICAL CHARACTERISTICS (Tj=25C unless otherwise stated) PARAMETER STATIC Gate trigger current Latching current Holding current On-state voltage Gate trigger voltage IGT IL IH VT VGT VD=12V;IT=10mA;gate open circuit VD=12V;IGT=0.5mA; RGK=1k VD=12V;IGT=0.5mA; RGK=1k IT=1A VD=12V;IT=10mA; gate open circuit VD=VDRM(max) ;IT=10mA ; Tj=125C; gate open circuit VD=VDRM(max) ;VR=VRRM(m ax) ;Tj=125C;RGK=1k VDM=67% VDRM(max); Tj=125C; exponential waveform;RGK=1k ITM=2A;VD=VDRM(max); IG=10mA;dIG/dt=0.1A/s VD=67% VDRM(max) ; Tj=125C;ITM=1.6A;VR=35V ;dITM/dt=30A/s; VD/dt=2V/s;RGK=1k 50 2 2 1.2 0.5 0.2 0.3 0.05 0.1 mA 200 6 5 1.35 0.8 A mA mA V V SYMBOL CONDITIONS MIN TYP MAX UNIT Off-state leakage current DYNAMIC Ciritical rate of rise of off-state voltage Gate controlled turn-on time Circuit commutated turn-off time ID,IR dVD/dt 25 V/s tgt tq 2 100 s s UTC UNISONIC TECHNOLOGIES CO., LTD. 2 UTC BT169 Ptot / W conduction angle degrees 30 60 90 120 180 form factor a 4 2.8 2.2 1.9 1.57 4 1.9 2.2 2.8 SCR Tc(max) / C a=1.57 ITSM / A 77 83 89 95 101 4 107 113 119 125 0 10 100 1000 Number of half cycles at 50Hz FIG.4 Maximnum permissible non-repetitive peak on-state current ITSM , versus number of cycles, for sinusoidal currents, f = 50Hz. IT(RMS) / A 2.0 1 2 6 10 IT 8 T 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 ITSM time Tj initial=25XC max 0.1 0.2 0.3 0.4 IF(AV) / A 0.5 0.6 0.7 FIG.1 Maximum on-state dissipation, P tot , versus average on-state current, I T(AV) , where a=form factor=I T(RMS) / IT(AV) ITSM / A 1000 1.5 100 IT 10 T ITSM 1.0 time Tj initial=25XC max 1 10s 100s T/s FIG.2 Maximum permissible non-repetitive peak on-state current ITSM ,versus pulse width tp,for sinusoidal currents, t p<=10ms. IT(RMS) / A 1.0 83XC 0.8 0.6 0.4 0.2 50 100 Tlead / C FIG.3 Maximum permissible rms current I lead temperature, Tlead 0 -50 0 150 T(RMS) 0.5 0 0.01 1ms 10ms 0.1 1.0 10 surge duration / s FIG.5 Maximum permissible repetitive rms on-state current I T(RMS) , versus surge duration, for sinusoidal currents, f= 50Hz; Tlead<=83XC VGT(Tj) VGT(25XC) 1.6 1.4 1.2 1.0 0.8 0.6 , versus 50 100 150 Tj / C FIG.6 Normalised gate trigger voltage V GT (Tj)/V GT( 25XC), versus junction temperature Tj 0.4 -50 0 UTC UNISONIC TECHNOLOGIES CO., LTD. 3 UTC BT169 IGT(Tj) VGT(25XC) IT / A 5 4 3 2 1 0 50 Tj / C 100 150 0 0 0.5 1.0 VT / V 1.5 Tj=125XC - - Tj= 25XC Vo=1.067V Rs=0.187 typ max SCR 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 2.0 FIG.7 Normalised gate trigger current GT(Tj)/IGT(25XC), I versus junction temperature Tj FIG.10 Typical and maximum on-state characteristic. IL(Tj) IL(25XC) 3.0 2.5 2.0 1.5 1.0 0.5 0 -50 0 50 Tj / C 100 150 100 Zth j-lead (K/W) 10 1 PD tp 0.1 0.01 10us 0.1ms 1ms t FIG.8 Normalised latching current L(Tj)/IL(25XC),versus I GK= junction temperature Tj, R 1K IH(Tj) IH(25XC) 10ms tp / s 0.1s 1s 10s FIG.11 Transient thermal impedance Zth j-lead, versus pulse width tp. 3.0 2.5 2.0 1.5 1.0 0.5 0 dVD/dt(V/us) 1000 100 RGK=1K 10 1 -50 0 0 0 Tj / C FIG.12 Typical, critical rate of rise of off-state voltage, dVD/dt versus junction temperature Tj. 50 150 50 100 150 Tj / C FIG.9 Normalised holding current H(Tj)/IH(25XC),versus I junction temperature Tj, R GK=1K UTC UNISONIC TECHNOLOGIES CO., LTD. 4 |
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